To conserve power, a system may change over to a power state including a power-on state, a sleep state, and a software-off state. Since the system can perform useful processes only in the power-on state, the system in the sleep state or the software-off state needs to perform the processes after changing over to the power-on state. Various depths are defined in the sleep state, and the deeper the depth is, the smaller the power consumption is and the longer the time (latency time) until changing over to the power-on state is. In the power-off state, power supply to most devices is stopped and thus the power consumption is minimized but the latency time is maximized.
When a system is in a power-on state, a central processing unit (CPU) or other device (devices other than the CPU that are connected with the computer will be simply be referred to as devices hereinafter) dynamically change over to various power states depending on operation states, thereby achieving reduction of power consumption. The CPU changes over between an active state and a sleep state when the system is in a power-on state, and a supply of power is stopped and the system lies in a stopped state when the system is in a sleep state or a soft-off state. The devices can change over between the active state and the sleep state or the stopped state when the system is in the power-on state. Many devices are stopped when the system is in the sleep state.
The CPU can execute processes when the system is in the active state, but first changes over to the active state in response to an interruption and then executes the processes when the system is in the sleep state. The sleep state of the CPU has various depths from the viewpoint of power consumption and latency time. The deeper the depth of the sleep state becomes, the lower the power consumption is and the longer the latency time is. An OS and a chip set control the depth of the CPU in the sleep state depending on a utilization rate of the CPU.
The CPU controls items which are factors of the power consumption such as core voltage, clock operation, clock frequency, PLL operation, and flash of cache context depending on the depth of the sleep state. Here, the utilization rate Y of the CPU can be calculated by the following expression, where Ui represents the ratio of a user mode time in idle processes, Ki represents the ratio of a kernel mode time in idle processes, and Et represents the elapsed time.Y=(1−(Ui+Ki)/Et)×100%
A state in which the utilization rate of the CPU is close to zero is generally referred to as an idle state, but is referred to as a utilization-rate idle state in this specification. Previously, the power consumption of a system was thought to be very small when the system changes over to the utilization-rate idle state. However, when the system is in the power-on state, the devices change over to predetermined power states through independent algorithms. Accordingly, even when the system changes over to the utilization-rate idle state, the system consumes constant power. For example, in certain systems, the power consumption of the system in the utilization-rate idle state may be about 5 W and the power consumption in the sleep state may be about 110 mW.
A CPU typically has a memory controller function, a graphics function, and the like installed therein in addition to the core functions, and thus the power consumption thereof tends to further increase. In recent years, the Intel® company has proposed a new power management technique in which plural power states (S0ix) are defined in the power-on state in order to reduce power consumption of a system in the utilization-rate idle state. In this technique, a CPU that can change over to a deeper sleep state is provided. A technique of changing over the CPU to a sleep state as deep as possible in the utilization-rate idle state by performing a delayable interruption and a DMA access together is introduced, or the devices are actively requested to change over to a stopped state.
The Microsoft® company recommends run-time idle state detection or S0 idle mounting for lowering the power of the devices in the idle state during operation of the system. The company proposes a technique of completely stopping the supply of power to the devices during operation of the system. This technique is also generally called Runtime D3. In the run-time idle state detection, the devices change over from the power-on state to a sleep state deeper than a conventional sleep state or to a stopped state. Therefore, by introducing such a new power management technique in the power-on state, the power consumption of the system is reduced to the vicinity of the power consumption in the suspended state in the future when the utilization rate of the CPU is lowered or the idle time of the device is raised in the system in the power-on state.